# What is negative voltage regulation

### Positive and negative Additional tension from DC voltage

1. Introduction (a.o. "Second Breakdown")

2. doubler and multiplier (Villard circuit)

3. Voltage doubler with CD4584B / MC14584B

4. More power with even more inverter blocks

5. Little "noise" and very stable

6. Negative voltage with voltage doubler

7. Two-phase voltage multiplier

### 1. Introduction (a.o. "Second Breakdown")

There are reasons that you need an additional positive or negative voltage with only a small current for part of a circuit. In this case it would often be shot at sparrows with cannons, if one would include the power supply unit to generate this additional voltage, which is mainly used to generate a high output. Especially when a switched-mode power supply is used for reasons of high efficiency, only direct voltages (DC voltages) are available anyway. So it's about transforming such a DC voltage into a higher or negative DC voltage. But wait, what's that supposed to mean? Since when can you transform DC voltages?

Right, that doesn't work and inventor Thomas Alva Edison already knew this back then in the pioneering days of electrical engineering, when he was in the infamous Current war hopelessly and fanatically defended his direct current against the pioneering alternating current of Nikola Tesla. Edison liked any means. He did not shrink from any atrocity. He had innocent animals and a person condemned to death brutally killed with alternating current. The first person on the electric chair! Here is another contribution to the chapter Electronics history (see index page) on this topic and beyond what Nikola Tesla did more than 100 years ago fundamentally and practically for the future of electrical engineering:

After this intended brief debauchery, back to this electronics mini-course. What is it about and what do you learn? As in the first electronics mini-course (1) of this type, it is shown how a square-wave generator and a few components can be used to generate a higher voltage than the operating voltage with low power. For stabilization, voltage regulators (LM317L and LM337L) are used here instead of Zener diodes (see: 1). But there is more to it than that. You learn how to use the same doubling method to generate an "artificial" negative voltage for a likewise low power, and this is followed by a voltage doubling for negative voltages. Instead of the CMOS timer module LMC555, as in (1), an IC from the digital CMOS family MC14xxxB (Motorola) or CD4xxxB (National Semiconductor) is used. It is the MC14584B or CD4584B. B stands for buffered and relates to the integrated output. Both ICs contain six Schmitt trigger inverters, they are pin-compatible and electronically identical.

This mini-course in electronics also explains the purpose of using so-called blocking capacitors, which are also known as backup capacitors. For the trainee, it is worth reading this chapter carefully, because this content is not only related to the topic of this electronics mini-course.

How to calculate the charging capacitors with regard to ripple voltage and load, you have to read in the first electronics mini-course (1) of this kind.

In this electronics mini-course it is also shown that to increase the performance of CMOS outputs, CMOS components can be connected in parallel, which in the case of components with bipolar transistors at the outputs, because of the so-called "second breakdown", not possible.

Finally, a little-known two-phase voltage multiplier is presented, of which I only know because I heard about it at a lecture. This idea fascinated me because it only needs half as many diodes as the well-known Villard circuit. I built this circuit on a test board, made a few experiments and roughly measured it. I am making this circuit and the results available here. Perhaps this idea will stimulate one or the other reader to develop further ideas about this idea. In short, the electronics mini-course begins! :-)

### 2. doubler and multiplier (Villard circuit)

In many textbooks on electrical engineering, not only is it explained how the rectifier-capacitor circuit in the form of the half-wave, midpoint and bridge rectifier works, it is often just as natural that it is explained how the voltage doubler and voltage multiplier, the so-called Villard circuit, works . Of course, this always requires an alternating voltage, as illustrated in Figure 2 with a mains transformer.

First compare the voltage doubler (part 2.1) with the first stage of the voltage multiplier (part 2.2), also from D1, D2, C1 and C2, so you can see that there is no difference. See small arrow. Both circuits are identical. Both parts generate, minus twice the diode flux voltage, twice the rectified peak value voltage from the secondary effective AC voltage Uac. C2 smooths this peak value voltage to a ripple-free DC voltage Udc, provided it is not loaded.

The unit of the voltage doubler can be expanded to a voltage multiplier up to very high voltages. Regardless of how long the multiplier chain is, the voltage across the capacitors is always the same. It should be noted, however, that the total capacity decreases drastically due to a large series connection and the smoothing property is also drastically impaired by the load. In addition, two diode flux voltages Ud drop per doubler stage, which has an impact with a low AC voltage Uac, even when Shottky diodes are used. Voltage multipliers are therefore only suitable where little to very little electricity is required. However, there is a simple and elegant way to do this when AC voltage is not available. More on this in the following chapter.

### 3. Voltage doubler with CD4584B / MC14584B

The voltage doubling in Figure 3 uses the integrated CMOS circuit MC14584B from ON Semiconductor (formerly Motorola) or CD4584B from National Semiconductor. This IC consists of six Schmitt trigger inverters. Consult the data sheet, available e.g. from Datasheetcatalog.com. The rectifier diodes BAT49 (D1, D2), which are used from Figure 3, are small Schottky diodes, which instead of silicon diodes with a threshold voltage of about 0.7 V only have about 0.25 V, which increases the efficiency of the circuit and the maximum level of the Output voltage improved.

These CMOS logic families can be used in an operating voltage range between +3 VDC and +15 VDC. The worst-case operating voltage is +18 VDC. If you value a long service life, it is advisable not to strive for this maximum voltage value. Even if this has not yet been achieved, the statistical service life is already reduced. Voltage values ​​around +12 VDC are best suited, because a low operating voltage of e.g. +5 VDC significantly reduces the drain-source resistances of the MOSFET output stages and this is precisely what has a particularly negative effect on the efficiency of a voltage doubler or even a voltage multiplier circuit. This circuit was implemented and used for an application with an operating voltage of +12 VDC. It was part of an analog measuring system that was operated with ± 12 VDC.

We come to the two circuits in Figure 3. Both have the square-wave generator in common, which requires one of the six Schmitt trigger inverters. How to dimension the frequency-determining components R1 and C2 for generating the frequency can be found in the data sheet. The other five inverters are connected in parallel on the input and output side in order to increase the output power fivefold. With this measure, the drain-source resistances of the MOSFETs of the inverter output stages are reduced to 1/5. The only thing that distinguishes the two parts 3.1 and 3.2 from each other is the wiring of C4. In 3.1 the cathode is on Ub and in 3.2 on GND. Provided that the input voltage Ub is blocked against GND with a capacitance Cx, which should be significantly larger than C4, the same amount of capacitance of C4 acts on the output Ub1 in both circuits. The only difference is that C4 in part 3.2 has to withstand the full open circuit voltage of Ub1, while C4 in 3.1 only has to withstand that of Ub1 minus Ub, and that corresponds to the value of Ub.

Using the example of part 3.1, we consider how the voltage doubles. When the output of the inverter block is low, C3 is charged from the input / operating voltage Ub via D1. This happens relatively quickly because the source Ub and D1 (conductive) are very low-resistance, but the source resistance of the inverter block is medium-resistance.

Blocking capacitor: As already indicated, it is assumed that Ub, in relation to C3 and C4, has to be blocked with a significantly higher capacity using an electrolytic capacitor Cx so that the charging process of C3 is not accompanied by a temporary Ub voltage drop. This is especially necessary when the circuit is battery-powered. It is not critical if Ub is generated with a stabilized power supply unit, which is usually the case. If the Ub source is too high-impedance, or rather too high-impedance in the low to medium frequency range, this would disrupt the function of the generator and there would be an unnecessarily high voltage drop under load on Ub1. This capacitance is indicated with Cx and is intended to show that this component does not have to be part of this circuit. It can be an electrolytic capacitor that blocks an entire circuit board where this doubler circuit is just part of a larger overall circuit. Blocking is understood to mean that the capacitance of the electrolytic capacitor ensures that the electrolytic capacitor takes over the power supply for a short time in the event of medium-frequency transient current loads. It can also be called a backup capacitor. A capacity of 100 µF is quite typical and sensible if the power supply unit is not on the same circuit board and itself has an electrolytic capacitor with a capacity of this order of magnitude at its output.

The blocking capacitor C1, on the other hand, is part of both doubler circuits in Figure 3 and serves the same purpose, but with much higher-frequency current transient processes. C1 does not serve as a temporary electricity supplier when charging the electrolytic capacitors C3 and C4. C1 serves as a very short-term supplier of electricity for the steep edges of the MOSFET output stages of the inverters. During the duration of this edge in the 100 ns range, both MOSFETs of the inverter output stage are conductive and if a low-inductance backup capacitor is not available near the IC, the generator may not work properly because this high-frequency transient process causes the Ub line may have a parasitic inductance that is too high. The consequence of this would be that the operating voltage would break down sensitively in the rhythm of the frequency of the generator for the duration of the edge. This would result in instability of the entire circuit.

When the output of the inverter block switches from low to high level, D1 blocks. D2 conducts because this high level shifts half of the charge in C3 via D2 to C4. They share the charge and if the capacities are the same, this means that the voltage across C3 and C4 is the same. If the inverter block switches to low again, C3 is recharged by D1. When switching to high again, there is another charge or voltage equalization between C3 and C4. Now with a voltage of 75% of the voltage of Ub. This is a simplification, because in reality the voltage across C4 is two diode flux voltages lower and if the period of the frequency of the square wave voltage is lower than about five times the value of the time constant from the source resistance of the inverter block and C3 or C4, there is also a voltage drop across the MOSFETs of the output stages of the inverters. So it's all a bit more complicated, but we don't need to worry about that in detail. It simply takes several clock phases until the voltage across C4 has practically approximated the voltage of Ub (part 3.1), minus the flow voltages of D1 and D2. When Ub1 is loaded, a voltage drops through the output resistance of the inverter block, which reduces the efficiency of the circuit. The voltage at Ub1 is doubled because the voltage over C4 is added to Ub (part 3.1).

The difference between the two partial images is already explained above, in which C4 in partial image 3.2 has to withstand twice as much tension as C3. But how does the almost double tension in part 3.2 come about? If the inverter block supplies a low level, C3 is loaded from Ub via D1, just as in part 3.1, but C4 is also loaded from Ub via D1 and D2. When the level is high, half of the charge is shifted from C3 to C4. At the next low level, C3 is charged again from Ub and at the next high level there is a renewed charge equalization between C3 and C4. So the voltage swings up over C4, whereby (the initial value) Ub always has to be added. In both circuit diagrams, charge is always first pumped from Ub (Cx) to C3 and then from C3 to C4 for each clock period. This functional principle is therefore also called the principle of the charge pump.

Part 4.1 repeats part 3.1. Diagram 4.2 illustrates in three pictures the voltages at the output of the inverter block (point 1), at point 2 and at Ub1. Output Ub1 is only very lightly loaded, so that the diode flux voltages are particularly noticeable. Point 1 shows the square wave voltage between Ub and GND and point 2 shows the same square wave voltage with Ub added and minus a diode flux voltage subtracted. Therefore the low level of the square wave voltage is one flow voltage below Ub. After a sufficient charge transfer transfer from C3 via D2 to C4, a smoothed voltage twice as high as Ub follows at Ub1, but reduced by an additional diode flow voltage from D2. See the bottom picture in diagram 4.2.

### 4. More power with even more inverter blocks

The parallel connection of inverters increases the efficiency by reducing the output resistance. Correspondingly more current can be drawn at Ub1 until the voltage collapses markedly. The maximum load on a single IC is 700 mW. It is advisable not to aim for this limit value for the sake of longevity. Half a watt is enough. The quiescent current per IC is specified with a maximum of 4 µA at an operating voltage of 15 VDC and a housing temperature of 25 degrees Celsius. Of course, this low current only applies if the inputs of all inverters have a defined logic state. The outputs then always have a defined logical state. If the level at an input is in the range of half the operating voltage, the current consumption of this inverter is greater, depending on the operating voltage somewhere in the mA range. This also applies to the inverter, which works as a square-wave generator, because its input always works within the hysteresis with a quasi-triangular signal, i.e. its mean voltage is half the operating voltage. The data sheet of the CD4584B (identical to CD40106B) illustrates this in the chapter Typical applications.

In addition, if you dimension an unnecessarily high frequency, the current or the power loss increases because the pulse duty factor is then relatively low. The duty cycle is the ratio of the very short current pulse, during the duration of the edge, to the period of the square wave signal. The current or the power loss that occurs as a result affects all inverters connected in parallel, because ultimately they all switch up and down synchronously. The data sheets indicate how to calculate this current. In practice, however, it is sufficient to know that a frequency around 100 kHz is ideal. The current or the power loss is not yet significantly increased when unloaded and the frequency is high enough to obtain low ripple voltages after the rectification with small capacities of the charging capacitors. These considerations apply, for example, to the circuits as shown in Figures 4 and 5.

If the power at the output of Ub1 is not sufficient according to the circuits in Figure 4, several of the same ICs can be connected in parallel without restriction, as Figure 5 illustrates. There may be more than the three ICs shown. The IC is very cheap. It should be pointed out at this point that if a distributor company only sells National and no ON Semiconductor products, it is often only the CD40106B that is offered instead of the CD4584B. So you have to look out for both products! Both ICs are identical. A data sheet applies to CD4584B and CD40106B.

If you connect many of these ICs in parallel, you may have to choose slightly higher values ​​for C3 and C4 so that the ripple voltage remains low enough with a higher current. It all depends on the application. The ripple voltage in the circuits with only one IC (Fig. 4) is around 40 mVpp (measured value) with a current of 10 mA at the output Ub1. In the chapter we will see whether this is a lot or a little with the use of downstream voltage regulators Little "noise" and very stable still get to know.

With Figure 6 we ask ourselves whether the individual inverters, even entire inverter blocks, can be connected in parallel at all. You can because the individual inverters consist of MOSFETs and not of bipolar transistors. Bipolar transistors cannot simply be connected in parallel without current negative feedback measures, because the transistor that draws a little more current and consumes power due to sample variations also heats up a little more than the others. This reduces its base-emitter threshold voltage, which again increases current, power and heating. With this local increase in current and power, the load on the bipolar transistors of the other inverters would be relieved, as a result of which the load on one inverter would increase further. We have positive thermal feedback that is unstable. A vicious circle until the power-dominating inverter says goodbye to the eternal electron-hunting grounds. The same effect occurs within the chip area of ​​a single bipolar transistor. There is a local increase in current, power and temperature on the chip surface and the transistor quickly breaks. That is why there are two slopes in the temperature performance diagram of bipolar transistors. The one that has to do with the effect just mentioned is called the "Second Breakdown".

With MOSFETs it is exactly the opposite. When it gets warm, the current and the power decrease where it is a bit warmer because the drain-source resistance increases. As a result, the current and the power are distributed over the entire involved MOSFET semiconductor surface, regardless of whether it is a single transistor or whether many are in use in parallel. We are dealing here with a thermal negative coupling and this is self-stabilizing.

### 5. Little "noise" and very stable

In Figure 7 we come back to the doubler circuit in part 3.1. The circuit in Figure 7 differs only in an additional passive low-pass filter of the second order, consisting of the inductance L and the capacitor C5. Such inductors, which look similar to a 1/2 watt resistor but are also available in SMD, are available from well-known electronics distributors such as Farnell. It doesn't have to be exactly 56 µH. The inductive resistance should be low so that the DC voltage drop across L is also low. At 3 ohms and a current of 30 mA it is just 90 mV, which is hardly of any importance. However, if you use whole inverter blocks with a correspondingly higher maximum output current, you may have to choose an inductance with lower ohmic losses.

The table in Figure 7 shows in the third and fourth columns how large the ripple and noise voltage UNOISE is as a function of the current Ib1. They are measured true RMS values ​​(values ​​of the square mean value). A distinction is made between a frequency bandwidth of 20 kHz (audio range) and 100 kHz. Since with a higher current Ib1 (column 1) the interference voltage at 100 kHz differs significantly more from that at 20 kHz than with a lower current, it can be seen that the ripple voltage has a greater impact on the higher current than the noise voltage. Column 5 shows the output voltage Ub1 as a function of the current Ib1 and in this context, column 2 shows the input current Ib and column 6 shows the efficiency.

In line 7 the input current Ib is 86 mA (column 2), which results in 1.03 W at an operating voltage Ub of 12 VDC. The efficiency is 68% (column 6). This results in a loss resistance of less than 0.33 W in the IC, because a small part falls on the two diodes D1 and D2 (about 30 mW) and on the inductance (about 5 mW). This means that less than half of the worst-case performance according to the data sheet is dropped across the IC, provided the IC is used in the DIL housing.

Figure 8 shows the same circuit from Figure 7 again, but expanded with an electronic voltage control with the little brother of the traditional LM317, the LM317L or LM317LZ in a small TO92 housing. The small table shows how high the maximum regulated output voltage Ub1 can be, taking into account the minimum dropout voltage of the voltage regulator, so that it still regulates properly. The formula for dimensioning the output voltage Ub1 comes from the data book and shows how R2 and R3 must be calculated. R2 should have a value of around 270 or 330 ohms. C6 is used for additional attenuation of the interference voltages. In the event of a short circuit at Ub1 or at the input of the LM317LZ, C6 requires the diode D4 so that C6 cannot discharge via the ADJ connection. D3 protects the LM317LZ from backflow of current, which can also lead to its destruction. This case occurs when a circuit with a relatively high capacitive load (e.g. many blocking capacitors) acts on Ub1 and the voltage doubler is switched off.

Now a few words about the interference voltage attenuation of the voltage regulator. The data sheets of the LM317 (LZ) and the LM337 (LZ) (for negative output voltages) each contain the diagram "Ripple rejection". This shows the additional damping of the ripple voltage by C6 and its dependence on the frequency of the ripple voltage. With the LM317 this frequency dependency is less pronounced than with the LM337 This is due to the fact that the internal no-load gain of the control loop is no longer as high at this high frequency as it is at a ripple frequency of 100 Hz from a bridge equalizer circuit on a mains transformer operated on the 230 VAC network. This is why it is necessary that low-ripple voltage is already provided at the input of the voltage regulator and this is done by the passive L-C5 low-pass filter.

### 6. Negative voltage with voltage doubler

With this chapter we come to the last two circuits of this type, but with negative regulated output voltages. The first circuit in Figure 9 shows how a single negative voltage and in Figure 10 a double negative voltage can be generated with just a few changes.

The circuit in Figure 9 is complementary to the circuit in Figure 8. The polarity is simply reversed. This affects all electrolytic capacitors, all diodes and instead of the positive voltage regulator LM317LZ, the negative LM337LZ, which is wired in the same way, is used. The table shows how high the maximum negative output voltage of the LM337LZ can be achieved with which current Ib1. The maximum currents can also be increased here with additional inverter blocks. The positive operating voltage is not doubled here, it is mirrored in the negative voltage range. Unloaded, there is almost the same voltage of Ub at point 1, but with a negative sign.

A negative doubling of the voltage can be achieved if the generator and the inverter block are fed in reverse. Connection 14 (VDD) is referenced with GND and connection 7 (VSS) is supplied with the negative operating voltage -Ub. At point 1, when there is no load, almost double the negative operating voltage is generated, which is related to GND and therefore the voltage regulator is related to GND. The same formula applies to the calculation of R2 and R3 as in Fig. 9. The number of inverters can also be expanded as required for this circuit. The maximum possible negative voltage values ​​as a function of the currents can be found in the adjacent table.

### 7. Two-phase voltage multiplier

We close this electronics mini-course with picture 11. This voltage multiplier works with two inverting square-wave signals. This saves one diode per stage, which halves the voltage loss compared to the principle of the Villard circuit. Originally this circuit was designed as part of a chip design. It had to power a photodiode with high voltage and very little current. This is an ideal application for such a circuit. The circuit on the chip is of course much simpler than the one shown in Figure 11. There it had a clock source and two tiny inverters that operated a diode-capacitor network integrated on the chip. The current for the photodiode was only a few microamps.

Figure 11 is nothing more than a test circuit with 5 outputs from A to E. If the anode of diode D6 is connected to A, Ub1 (output voltage) has twice the voltage of Ub (input voltage). At B it is three, etc. and at E six times the output voltage. The loss voltages of the Schottky diodes D1 to D6 are now not taken into account. See the diagram with the signals. The sole purpose of D6 is to ensure that the square-wave voltage is rectified and smoothed to the voltage peak value with no or light load.

Because this circuit is operated with 5 VDC, I used a six-fold Schmitt trigger inverter from the HCMOS family of the type 74HC14 in the test setup. More details, such as the calculation of the frequency of the square wave generator, can be found in the data sheet.

The evaluation follows:

Contact point Ub1 load current Ib1 input current Ib from D6 (V) (mA) (mA) --------------------------------- --------------------- A 10 0 0.4 9.5 1 2.5 9.2 5 10 8.9 10 20.5 8.3 20 41 7.7 30 61 B 15 0 0.4 14.3 1 3.5 13.7 5 15.6 13.1 10 30.2 11.8 20 60.7 C 20 0 0.4 18.8 1 4.4 18.3 2 8.5 17.0 5 20.4 16.4 10 41 D 25 0 0.4 23.6 1 5.4 23.2 2 10.4 22.2 5 25.5 20.5 10 50.4 E 30 0 0.4 28.2 1 6.5 27.6 2 12.5 25.8 5 30.5 23.0 10 61 The no-load current of 0.4 mA results at a generator frequency of 100 kHz, at 10 kHz are it 0.1 mA.